HYS=DISABLE, INV=INPUT_NOT_INVERTED, OD=DISABLE, S_MODE=BYPASS_INPUT_FILTER, CLKDIV=IOCONCLKDIV0, MODE=INACTIVE_NO_PULL_DO
I/O configuration for port PIO2
| FUNC | Selects pin function. |
| MODE | Selects function mode (on-chip pull-up/pull-down resistor control). 0 (INACTIVE_NO_PULL_DO): Inactive (no pull-down/pull-up resistor enabled). 1 (PULL_DOWN_RESISTOR_E): Pull-down resistor enabled. 2 (PULL_UP_RESISTOR_ENA): Pull-up resistor enabled. 3 (REPEATER_MODE): Repeater mode. |
| HYS | Hysteresis. 0 (DISABLE): Disable. 1 (ENABLE): Enable. |
| INV | Invert input 0 (INPUT_NOT_INVERTED): Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). 1 (INPUT_INVERTED_HIGH): Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). |
| RESERVED | Reserved. |
| OD | Open-drain mode. 0 (DISABLE): Disable. 1 (ENABLED): Enabled. Open-drain mode enabled. This is not a true open-drain mode. |
| S_MODE | Digital filter sample mode. 0 (BYPASS_INPUT_FILTER): Bypass input filter. 1 (1_CLOCK_CYCLE): 1 clock cycle. Input pulses shorter than one filter clock are rejected. 2 (2_CLOCK_CYCLES): 2 clock cycles. Input pulses shorter than two filter clocks are rejected. 3 (3_CLOCK_CYCLES): 3 clock cycles. Input pulses shorter than three filter clocks are rejected. |
| CLKDIV | Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved. 0 (IOCONCLKDIV0): IOCONCLKDIV0. Use IOCON clock divider 0. 1 (IOCONCLKDIV1): IOCONCLKDIV1. Use IOCON clock divider 1. 2 (IOCONCLKDIV2): IOCONCLKDIV2 Use IOCON clock divider 2. 3 (IOCONCLKDIV3): IOCONCLKDIV3. Use IOCON clock divider 3. 4 (IOCONCLKDIV4): IOCONCLKDIV4. Use IOCON clock divider 4. 5 (IOCONCLKDIV5): IOCONCLKDIV5. Use IOCON clock divider 5. 6 (IOCONCLKDIV6): IOCONCLKDIV6. Use IOCON clock divider 6. |
| RESERVED | Reserved. |